The present invention generally relates to thermoelectric cooling. More particularly, the invention is directed to methods for fabricating semiconductor devices having integrated circuits and integrated thermoelectric coolers for thermal management of the integrated circuits and semiconductor devices made from such methods.
Sub-ambient cooling is conventionally accomplished through gas/liquid vapor phase compression based refrigeration cycles using Freon type refrigerants to implement the heat transfers. Such refrigeration systems are used extensively for cooling human residences, perishable items, and vehicles. Sub-ambient cooling is also often used with major electronic systems such as mainframe, server and workstation computers. Though vapor compression cooling can be very efficient, it does require significant moving hardware. Vapor compression cooling systems, at a minimum, include a compressor, a condenser, an evaporator, and related coolant transfer plumbing. As a result of the complexity and associated high cost, vapor compression cooling has not found material acceptance in small cooling applications, such as personal computers, integrated circuits, etc.
The fact that CMOS logic can operate significantly faster as the temperature decreases has been well known for many years. For example, when CMOS logic devices are operated at xe2x88x9250xc2x0 C. their performance is improved by 50 percent over room temperature operation. Liquid nitrogen operating temperatures, in the range of xe2x88x92196xc2x0 C., have shown 200 percent performance improvements. Similar benefits have been shown to accrue for integrated circuit wiring, where metal wiring resistance decreases by a factor of 2 for integrated circuits operated at xe2x88x9250xc2x0 C. in comparison to room temperature operation. These performance improvements rival the recent technological breakthrough of using copper wiring in integrated circuits to reduce interconnect resistance and thereby effectively increase the operating frequencies attainable. Thus, sub-ambient temperature operation of integrated circuit logic devices, such as field effect transistors, as well as interconnect wiring can improve integrated circuit performance. This performance enhancement then poses the question of how to accomplish such cooling in the confines of the ever decreasing size and materially shrinking cost environment of microelectronics.
FIG. 1 schematically depicts a conventional Peltier type thermoelectric element (TE) 1 with DC power supply 2 creating the electric field across TE 1 while at a load current 3. The desired heat transfer is from cold sink 4, at temperature Tcold, to hot sink 6, at temperature Thot. As indicated in the equation of FIG. 1, the net heat energy transported is composed of three elements, the first representing the Peltier effect (thermoelectric) contribution, the second defining negative Joule heating effects, and the third defining negative conductivity effects. The thermoelectric component is composed of the Seebeck coefficient, the temperature of operation (Tcold) and the current being applied. The Joule heating component reflects that roughly half the Joule heating goes to the cold sink and remainder to the hot sink. Lastly, the negative component attributable to thermal conduction represents the heat flow through the Peltier device, as defined by the thermal conductivity of the Peltier device, from the hot sink to the cold sink. See equation (1).
q=xcex1TcoldIxe2x88x92(xc2xd)I2Rxe2x88x92Kxcex94Txe2x80x83xe2x80x83(1)
International Business Machines (IBM) Corporation, assignee of the present invention, has made advances with thin film implementations and miniaturization of thermoelectric coolers. See U.S. patent application Ser. No. 09/458,270 having the title xe2x80x9cElectrically-Isolated Ultra-Thin Substrates For Thermoelectric Coolersxe2x80x9d and U.S. patent application Ser. No. 09/458,271 having the title xe2x80x9cThermoelectric Cooling Apparatus And Method For Maximizing Energy Transportxe2x80x9d both applications of which are hereby incorporated by reference. Thin film implementations and miniaturization of thermoelectric coolers provides high cooling flux scaling with the smaller geometries to provide cooling in the range of 2-3 W/cm2 to 100 W/cm2 with high entropy gradients and lower thermal conductivities. Use of thin film implementations yields higher reliability MTBF (mean time between failures) of greater than 106 hours, lower cost in the order of less than 100¢/W and ease of constructing multistage configurations wherein nanoscopic coolers can be operated in parallel for large cooling capacity and high efficiency.
With these advances many problems can be solved. One such problem is thermal management across an integrated circuit such as a relatively large processor chip. For example, in operation, most processor chips have nonuniform temperature distribution across the chip wherein the portion of the chip having the Arithmetic Logic Unit (ALU) may operate at one temperature while the portions of the chip having the cache or cache interfaces may operate at another temperature. Nonuniform temperature distribution across the chip presents a myriad of problems including problems with performance, processing speed and reliability. To avoid these problems, uniform temperature distribution across the chip is needed.
Present methods for addressing the problem of thermal management of integrated circuits and associated problems such as described above have proven to be costly and difficult to implement. Thus a need exists for an improved low cost method of addressing these problems by cooling integrated circuits using, in part, the advances made by IBM Corporation with thin film implementations and miniaturization of thermoelectric coolers as mentioned above.
The present invention provides for an improved low cost method of fabricating a semiconductor device having integrated circuits and integrated thermoelectric coolers for cooling the integrated circuits and a semiconductor device made using such method.
In one form, the invention relates to a method of fabricating a semiconductor device comprising forming an integrated circuit on a front side of a substrate and forming an integrated thermoelectric cooler capable of cooling the integrated circuit on a back side of the substrate.
In another form, the invention relates to a semiconductor device made using the method described above comprising a substrate having a front side and a back side, an integrated circuit formed on the front side of the substrate and an integrated thermoelectric cooler formed on the back side of the substrate capable of cooling the integrated circuit.
In one particularized form of the invention, a composite semiconductor device structure is fabricated by forming an integrated circuit on a front side of a first substrate and forming an integrated thermoelectric cooler on a back side of the first substrate. A thermal sink of semiconductor material capable of absorbing heat from the integrated circuit is formed on the back side of a separate second substrate. N-type thermoelectric elements are formed on contacts connected to doped regions in the first substrate. P-type thermoelectric elements are formed on contacts connected to doped regions in the second substrate forming a thermal path of semiconductor material to a thermal sink capable of dissipating heat. The p-type and n-type thermoelectric elements are bonded to complementary contacts formed on the first and second substrates, respectively, by a flip-chip soldering process.
In yet another particularized form of the invention, a semiconductor device includes multiple thermoelectric elements formed in selective patterns to extract heat at different rates from different portions of the integrated circuit to thereby achieve substantially uniform temperature distribution across the integrated circuit.
These and other features of the invention will be more clearly understood and appreciated upon considering the detailed embodiments described hereinafter.